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Registro Completo |
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Biblioteca(s): |
Embrapa Agricultura Digital. |
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Data corrente: |
11/07/1996 |
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Data da última atualização: |
17/08/2007 |
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Autoria: |
RODA, V. O.; LIN, T. T. Y. |
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Título: |
On the effect of spare positioning on the reconfigurability of two-dimensional processor arrays. |
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Ano de publicação: |
1995 |
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Fonte/Imprenta: |
In: SIMPÓSIO DE COMPUTADORES TOLERANTES A FALHAS, 6.; CONGRESSO DA SOCIEDADE BRASILEIRA DE COMPUTAÇÃO, 15., 1995, Canela. Anais ... Porto Alegre: UFRGS, Instituto de Informática, 1995. |
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Páginas: |
p.77-90. |
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Idioma: |
Inglês |
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Conteúdo: |
In this work investigated some reconfiguration and routing aspects of fault tolerant processing arrays. An interconnection topology with disjoint busses for the horizontal and vertical connections, called "double bus array", was adopted. Reconfiguration of the array after diagnosis encompasses the allocatioon of spare units to replace the faulty processors, renaming of the processor elements and interconnecting (routing) data through the operating processors acording to the initial specified operation. We fully simulated reconfiguration and routing for arrays of size N, from 5 to 25 processors and faults from 1 to 2N +1. Faults were generated randomly to simulate defects on a wafer. We present in this paper the results of the simulations and discuss the possible reasons for reliability improvements. |
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Categoria do assunto: |
-- |
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Marc: |
LEADER 01371naa a2200145 a 4500
001 1002906
005 2007-08-17
008 1995 bl uuuu u00u1 u #d
100 1 $aRODA, V. O.
245 $aOn the effect of spare positioning on the reconfigurability of two-dimensional processor arrays.
260 $c1995
300 $ap.77-90.
520 $aIn this work investigated some reconfiguration and routing aspects of fault tolerant processing arrays. An interconnection topology with disjoint busses for the horizontal and vertical connections, called "double bus array", was adopted. Reconfiguration of the array after diagnosis encompasses the allocatioon of spare units to replace the faulty processors, renaming of the processor elements and interconnecting (routing) data through the operating processors acording to the initial specified operation. We fully simulated reconfiguration and routing for arrays of size N, from 5 to 25 processors and faults from 1 to 2N +1. Faults were generated randomly to simulate defects on a wafer. We present in this paper the results of the simulations and discuss the possible reasons for reliability improvements.
700 1 $aLIN, T. T. Y.
773 $tIn: SIMPÓSIO DE COMPUTADORES TOLERANTES A FALHAS, 6.; CONGRESSO DA SOCIEDADE BRASILEIRA DE COMPUTAÇÃO, 15., 1995, Canela. Anais ... Porto Alegre: UFRGS, Instituto de Informática, 1995.
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Registro original: |
Embrapa Agricultura Digital (CNPTIA) |
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| 10. |  | JORGE, L. A. C.; MINGHIM, R.; NONATO, L. G.; BISCEGLI, C. I.; PEDRINO, E. C.; RODA, V. O.; PAIVA, M. S. V. 3D Reconstruction, visualization and volume calculation of fruits. In: COMPUTER GRAPHICS INTERNATIONAL - CGI, 2007. Petrópolis, RJ. Papers... [Porto Alegre: UFRGS, 2007]. Não paginado. Anais.| Tipo: Artigo em Anais de Congresso / Nota Técnica |
| Biblioteca(s): Embrapa Instrumentação. |
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| Registros recuperados : 10 | |
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